Recently, memory devices accommodate higher and higher frequency signals, and in this context, it is required that the input and output be driven without noise or delay even if the address transition becomes faster. An I/O line equalization circuit is used almost in every memory device for optimizing the equalization time when an address transition signal is generated to output an equalization pulse.
However, the equalization pulse generator which is used in the conventional memory device is unsuitable in the equalization time for the case where the address transition is fast. Therefore, it became an unstabilizing problem in driving the I/O line.
An address transition pulse generating circuit is used in the conventional memory devices as disclosed in U.S. Pat. No. 4,614,883.
As shown in FIG. 1, the equalization pulse generating circuit is constituted as follows. That is, a Plurality of MOS transistors are connected to address transition signals. Thus, if the address transition signal is shifted, then an EQ signal is formed, so that the I/O lines would be equalized.
FIG. 2 is a timing chart for the equalization pulse generating circuit for the conventional memory devices.
The conventional technique will be described referring to FIGS. 1 and 2.
As shown in FIG. 1, this conventional circuit includes a first NOR circuit section A consisting of five transistors Q(A), Q(B), Q(C), Q(D) and Q(E);
a second NOR circuit section B consisting of inverters INV(A), INV(B), INV(C) and INV(D), NAND gates ND(A) and ND(B), and a NOR gate NOR(A);
a latching section C consisting of two inverters INV(E) and INV(F);
a charging section D consisting of a NAND gate ND(C), an inverter INV(G) and two transistors Q(F) and Q(G);
a delay circuit section E consisting of an inverter INV(H), a delay circuit T and a NOR gate NOR(B); and
an inverter INV(I).
In the first NOR gate circuit section A, the gate of the transistor Q(A) is connected to an inverted chip selecting signal CSD, and the gate of the transistor Q(B) receives an address transition signal ATXO. Further, the gate of the transistor Q(C) receives an address transition signal ATX1, and the gate of the transistor Q(D) receives an address transition signal ATX2, while the gate of the transistor Q(E) receives an address transition signal ATX3. The sources of the transistors Q(A), Q(B), Q(C), Q(D) and Q(E) are all connected to Vss, while the drains of these transistors are connected to a node N1.
In the latching section C, the input terminal of the inverter INV(E) is connected to the node N1, and the output terminal of the inverter INV(E) is connected to the input terminal of the inverter INV(F), while the output terminal of the inverter INV(F) is connected to the node N1 in turn.
In the second NOR circuit section B, the input terminal of the inverter INV(D) is connected to an address transition signal ATXO, while the input terminal of the inverter INV(C) is connected to an address transition signal ATX1. Further, the output terminal of the inverter INV(D) and the output terminal of the inverter INV(C) are connected respectively to the two input terminals of the NAND gate ND(A). The input terminal of the inverter INV(B) is connected to an address transition signal ATX2, while the input terminal of the inverter INV(A) is connected to an address transition signal ATX3. Further, the output terminals of the inverters INV(A) and INV(B) are connected respectively to two input terminals of the NAND gate ND(B). Further, the output terminals of the NAND gates ND(A) and ND(B) are connected respectively to two input terminals of the NOR gate NOR (A), while an output signal INH of the NOR gate NOR(A) is connected to the charging section D.
The input terminal of the inverter INV(I) is connected to the node N1, while the output terminal of the inverter INV(I) generates equalization pulses EQ.
In the delay circuit section E, the input terminal of the inverter INV(H) is connected to the output terminal of the inverter INV(I), and the output terminal of the inverter INV(H) is connected to the input terminal of the delay device T. The chip selecting signal CSD and the output terminal of the delay device T are connected to two input terminals of the NOR gate NOR(B), while the output signal SRE of the NOR gate NOR(B) is connected to the charging section D.
In the charging section D, the output terminal of the NOR gate NOR(A) of the second NOR circuit section B and the output terminal of the NOR gate NOR (B) of the delay circuit section E are connected respectively to two input terminals of the NAND gate ND (C) . The output signal RE of the NAND gate ND(C) is connected to the input terminal of the inverter INV(G) and to the gate of the transistor Q(F). The source of the transistor Q(F) is connected to Vdd, and its drain is connected to the node N1. The output terminal of the inverter INV(G) is connected to the gate of the transistor Q (G), and the drain of the transistor Q(G) is connected to Vdd, while its source is connected to the node N1.
The conventional circuit constituted as described above operates in the following manner.
When the chip selecting signal is enabled in a state where the address transition did not occur, the initial values are as follows.
As shown on the left side of FIG. 2, when a chip selecting signal is generated as the signal CSD being shifted from high to low, the output of the NOR gate NOR(B) becomes high, and therefore, the signal SRE becomes high. Since the four address transition signals are all low, the outputs of the NAND gates ND(A) and ND(B) become low. Consequently, the inputs of the NOR gate NOR(A) become all low, with the result that the output signal INH of the NOR gate NOR(A) becomes high.
The two signals INH and SRE which are inputted into the NAND gate ND(C) are all high, and therefore, the output signal RE of the NAND gate ND(C) becomes low. Therefore, the node N1 comes to have a potential of Vdd.
When the high signal of the node N1 passes through the inverter INV(I), the output signal EQ becomes low. This signal is inverted by the inverter INV(H), and the inverted signal is supplied to the input terminal of the NOR gate NOR(B) after being delayed for a certain time period by the delay device T. Therefore, the signal SRE becomes low again after a certain time period. This low signal is supplied to the input terminal of the NAND gate ND(C), and therefore, the signal RE becomes high.
Therefore, as described above, the initial values become as follows. That is, the node N1 becomes high, the signal EQ becomes low, the signal SRE becomes low, the signal RE becomes high, and the signal INH becomes high.
First, in the case where the address transition signal ATXO is high, the circuit operates in the following manner.
When the address transition signal ATXO becomes high at a position "A", the transistor Q(B) is turned on, with the result that the node N1 comes to have a potential Vss. This signal is inverted by the inverter INV(I), with the result that the output signal EQ becomes high.
The address transition signal ATXO is inverted by the INV(D) so as to become low, and this signal is connected to the input terminal of the NAND gate ND (A). If any one of inputs for a NAND gate is low, then its output becomes high. Therefore, the output of the NAND gate ND (A) becomes high so as to be supplied to the input terminal of the NOR gate NOR(A). If any one of inputs for a NOR gate is high, then its output becomes low, and therefore, the output of the NOR gate NOR(A) becomes low. Thus the signal INH becomes low.
The high signal which is outputted from the inverter INV(I) is inverted by the inverter INV(H) so as to become low, and then, passes through the delay device T. Therefore, the output of the delay device T is maintained in a high state until the signal EQ is inverted and passes through the delay device T. The output of the delay device T becomes low after the elapsing of the delayed time. Therefore, the signal which has passed through the delay device T becomes high at a time "A", and becomes low at a time "B" shown in FIG. 2.
The signal which has passed through the delay device T is inputted into the NOR gate NOR(B) together with the chip selecting inverted low signal CSD. Thus the signal SRE which is an output of the NOR gate NOR(B) is maintained at a low level as much as the delayed time period of the delay device T.
If the signal SRE is low, the input of the NAND gate ND(C) becomes high. This means that the PMOS transistor Q(F) and the NMOS transistor Q(G) are all in a turned-off state, and therefore, the potential of the node N1 becomes low.
Under this condition, the address transition signal ATXO has become low, while the equalization pulse EQ is an inverted signal of the node N1. Therefore, it maintains a high state up to a time "B" at which the signal SRE becomes high.
The signal SRE becomes high at the time "B" after being delayed, while the signal INH becomes high from the moment when the address transition signal ATXO becomes low. Therefore, the two signals which are inputted into the NAND gate ND(C) become high, with the result of the signal RE becoming low.
The transistor Q(F) is turned on by the low signal RE, and the signal RE is inverted by the inverter INV(G). Consequently, the transistor Q(G) is turned on, and the node N1 becomes high.
If the node N1 becomes low, the signal EQ is outputted as inverted, i.e., with a low level.
Next, in the case where address transition signals are generated with a short time interval, the circuit operates in the following manner.
The address transition signal ATXO returns to a low level at the time "B" of FIG. 2. Further, the signal EQ is high, and the address transition signal ATXO is low. Therefore, when the signal SRE becomes high in a state with the signal INH in a high level, the node N1 is shifted to a potential of vdd. If another address transition signal ATX1 becomes high at the time "B", the transistor Q(C) is turned on, so that the node N1 would be connected to a potential of Vss. That is, the node N1 is simultaneously connected to the potential Vdd and the potential Vss, with the result that the power source is short-circuited.
Therefore, the address transition signal ATX1 becomes high, with the result that the signal INH becomes low, and that the signal RE becomes high, thereby turning off the transistors Q(F) and Q(G). Under this condition, until the node N1 is prevented from becoming a Vdd potential, and at the time point when the address transition signal ATX1 becomes high, the node N1 makes a dc current flow from a Vdd potential to a Vss potential during the delayed time.
If the next address transition signal ATX1 is shifted to a high state in a fast manner, the node N1 causes a short-circuit between the power sources. Therefore the conventional equalization pulse generating circuit loses its effectiveness.